The present invention relates to a data processor and a data processing method for a path metric updating process, that is, a principle process in Viterbi decoding.
Recently, a variety of systems for rapidly transferring data such as image data and speech data have been introduced into digital data communications. In such data transfer, an algorithm called Viterbi decoding is generally adopted for decreasing bit errors in the data. On the other hand, in accordance with improvement in the performance of a digital signal processor (hereinafter referred to as the DSP), Viterbi decoding algorithm is generally executed by a DSP.
Update of path metrics is one of the main processes in Viterbi decoding. In this update process, path metrics corresponding to respective states of a convolutional encoder are updated in order to decode signals encoded by the convolutional encoder at a receiver side. Specifically, the update process includes a series of steps as follows: Pre-update path metrics and corresponding branch metrics are added to each other with regard to two states, and the results of these two additions are compared with each other, so that the smaller result is selected as an updated path metric. Such a series of calculations are designated as an ACS (add compare select) processing because addition, calculation and selection are continuously executed. In general, such an update process of the path metrics is executed several tens through several hundreds times.
In the conventional update process of the path metrics, for obtaining one updated path metric, one pre-update path metric is first read from a memory, the read path metric is added to a corresponding branch metric and the result of the addition is stored in a register. Next, another pre-update path metric is read from the memory, the read path metric is added to a corresponding branch metric and the result of the addition is stored in the register. Then, the two data stored in the register are compared with each other so as to select an updated path metric.
However, in the conventional update process of the path metrics, a large number of steps are required for obtaining one updated path metric. This prevents Viterbi decoding from being executed at a higher speed.
Furthermore, in order to obtain one updated path metric, the memory for storing the pre-update path metrics is required to be accessed as frequently as twice. This not only prevents Viterbi decoding from being executed at a higher speed but also prevents power consumption of the processor from decreasing. In a DSP, power consumed through access to a memory occupies a very large proportion in the total power consumption of the DSP, and hence, decrease of the frequency of the memory access can largely decrease the total power consumption of the DSP.